Marco Ottavi

Department of Electronic Engineering,
University of Rome Tor Vergata
Rome, Italy, 00133
ottavi@ing.uniroma2.it

Bio:
Marco OttaviMarco Ottavi (M’04-SM’10) is Associate Professor at University of Rome Tor Vergata with National Scientific Qualification for Full Professor in Electronic Engineering. He joined the University of Rome Tor Vergata as the recipient of a prestigious “rientro dei cervelli” (Reverse Brain Drain) fellowship awarded by the Italian Ministry of University and Research. Previously he was a Senior Design Engineer at Advanced Micro Devices (Boston Design Center) and a postdoctoral research associate at Sandia National Laboratories and at the Department of Electrical and Computer Engineering of Northeastern University in Boston. He received the Ph.D. in Microelectronics and Telecommunications Engineering from University of Rome Tor Vergata and the Laurea degree in Electronic Engineering from University of Rome La Sapienza. His research focuses on the various aspects of manufacturability and reliability of electronic systems at nanoscale. On these topics he teaches a graduate course at the University and has published over 120 contributions (Scopus: H-index=20) to international conferences and peer-reviewed journals. He serves as reviewer for many IEEE journals and highly cited conferences, he has been a Guest Editor of two Special Issues of IEEE Transactions on Nanotechnology and an Associate Editor of IEEE Transactions on Emerging Topics in Computing. He also serves as organizer, member of the technical program committee, and reviewer of several IEEE journals and conferences. From 2011 to 2015 he was the chair of the European project COST MEDIAN (Manufacturable and Dependable Multicore Architectures at Nanoscale). In 2012 he was part of the funded UK- EPSRC Grant “Yield and reliability enhancement techniques for novel memory devices” focusing on novel memristor based architectures. Since 2017 he is the co-PI of the Leverhulme Trust (UK) grant “MONITOR: A Self-Repairable Memristive Gas Sensor Array”. He is a senior member of IEEE and a member of the HiPEAC Network of Excellence.