From the May 2016 issue of IEEE Transactions on Nanotechnology
by Hamidreza Aghasi ; Rouhollah Mousavi Iraei ; Azad Naeemi ; Ehsan Afshari
T-NANO, Vol. 15, Issue 3, pp. 356 – 366, May 2016.
Abstract: We present a new circuit for non-Boolean recognition of binary images. Employing all-spin logic (ASL) devices, logic comparators and non-Boolean decision blocks for compact and efficient computation are designed. By manipulation of fan-in number in different stages of the circuit, the structure can be extended for larger training sets or larger images. Operating based on the main similarity idea, the system is capable of constructing a mean image and compare it with a separate input image within a short decision time. Taking advantage of the nonvolatility of ASL devices, the proposed circuit is capable of hybrid memory/logic operation. Compared with the existing CMOS pattern recognition circuits, this paper achieves a smaller footprint, lower power consumption, faster decision time, and a lower operational voltage.