Special Section on IEEE Trans. on Computers and IEEE Trans. on Nanotechnology
The IEEE Transactions on Computers and IEEE Transactions on Nanotechnology seek original manuscripts for a Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems scheduled to appear in the issue of March 2016.
The topics of interest for these special sections include, but are not limited to:
- Yield Analysis and Modeling
Defect/Fault analysis and models; statistical yield modelling; critical area and metrics.
- Testing Techniques
Built-in self-test; delay fault modelling and diagnosis; testing for analogue and mixed circuits; signal and clock integrity.
- Error Detection, Correction, and Recovery
Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques.
- Dependability Analysis and Validation
Fault injection techniques and environments; dependability characterization.
- Defect and Fault Tolerance
Reliable circuit/system synthesis; radiation hardened/tolerant processes & design.
- Variability at nanoscale
Variation of electrical characteristics of nanoscale devices due to process, aging, temperature etc.
- Fault modelling of emerging devices
Modeling and analysis of temporary and permanent faults in CNTs, QCA, DNA, RTDs, SETs, molecular devices.
- Yield and reliability of non-CMOS based memories
Defect and fault in PCM RAM, Spin-Transfer-Torque MRAM, memristors based memories etc.
- Design tools for DFT
New design tools for Defect and Fault Tolerance; applicability of existing algorithms and method to novel technologies; Design of novel tools for next generation nanotechnology systems.
- Case studies
Applications to automotive, railway, avionics, industrial control, biomedicine, space.
The submitted papers must describe original research which is not published nor currently under review by other journals or conferences. Extended conference papers should contain at least 40% new material and will pass through the normal review process. Authors are invited to submit manuscript focused on gate and higher system levels directly to TC (https://mc.manuscriptcentral.com/tc-cs) and papers focused on circuit and lower levels directly to TNANO (https://mc.manuscriptcentral.com/tnano). However, authors should be aware that papers will be published in TC or TNANO depending on the technical content of the paper and the availability of space. The selection will be at the discretion of the Editor-in-Chiefs of the respective Transactions.
With this premise, authors must clearly indicate their preference for publication in the cover letter. Please address all correspondences regarding this Special Section to the Guest Editors (email: dft_joint_special_section AT ing DOT uniroma2 DOT it). To increase the impact and visibility of their work, authors of accepted papers will be requested to prepare a short “abstract video” of their manuscript to be published as supplemental material in the TC or TNANO websites.
|Submission||February 1, 2015|
|First decision to authors||April 15, 2015|
|Revision due (if needed)||May 15, 2015|
|Final notification of acceptance/rejection||July 15, 2015|
|Publication material for final manuscripts due||July 30, 2015|
|Special Section publication||issue March 2016|
- Cristiana Bolchini (Politecnico di Milano, Italy)
- Sandip Kundu (University of Massachusetts, Amherst, USA)
- Salvatore Pontarelli (CNIT – Italian Inter-University Consortium of Telecommunications, Italy)
Downloadable Call for Papers pdf.