Back End of Line (BEOL) process is the second portion of IC fabrication where devices or components get interconnected with wiring on the wafer. Particularly in advanced technology nodes, the requirements of high integration density, performance, and new functionalities make it imperative to optimize BEOL process. Moreover, BEOL layers can easily implement heterogeneous integration of multiple functions and various fabrication processes on the same chip. To fully achieve these goals, BEOL compatible materials and devices are urgently needed. BEOL compatibility typically means chemical compatibility (non-corrosive and non-reactive) and thermal compatibility (< 400 deposition temperature) with Front End of Line (FEOL) layers for the materials deposition and device fabrication processes. This special section aims to cover research progress and present a forward-looking discussion of BEOL compatible materials, devices and technologies. It will also cover system level innovations regarding architectures, interconnects and packaging through the exploration of BEOL compatible materials and devices. The special section will discuss the selection and optimization of materials for BEOL compatible devices and circuits to achieve high performance, energy-efficient computing. The special section will also emphasize on the novel structure and design that integrate different functions on one chip through BEOL compatible technique, like near-memory computing, electronic-photonic integration and integrated sensors in computing nano-systems. The issue will also cover BEOL heterogeneous integration with mainstream semiconductor technologies. The IEEE Transactions on Nanotechnology solicits contributed articles that will discuss the above. Topics of interest include, but are not limited to:
- Advanced interconnects and isolation materials and processes.
- Monolithic 3D integration.
- Heterogenous integration.
- Emerging materials and devices for BEOL.
- New computing architecture through BEOL.
- Reliability and failure analysis for BEOL.
- BEOL Memory technologies.
- Photonic BEOL integration.
- Modeling, simulation and related software for BEOL process.
Manuscripts for the TNANO Special Section must be submitted on-line using the IEEE TNANO manuscript template. Follow the guidelines (https://tnano.org/), and submit your paper to ScholarOne Manuscripts at http://mc.manuscriptcentral.com/tnano, indicating in the cover letter that you wish the paper to be considered for “IEEE Transactions on Nanotechnology (TNANO) Special Section on the “Nanoscale Architectures Symposium (NANOARCH 2021)”. Please note that the type of submissions is Regular Manuscripts, i.e., 4 to 6 pages in the two-column IEEE format, which includes figures, tables, and references. On submission to TNANO, authors should select the “Special Issue” manuscript type instead of “Regular Paper.”
Manuscripts will be subject to the standard competitive and constructive peer-review TNANO criteria with no article publishing charges. Accepted papers are published on the web in IEEE Xplore as soon as they are submitted in final form. Web-published papers have a DOI (Digital Object Identifier), and are fully citable and downloadable.
- Submission deadline: May 31st, 2022
- First decision (accept/reject/revise): August 30th, 2022
- Revised papers submission: October 31st, 2022
- Final decision: December 30th, 2022
- Prof. Dominique Baillargeat, University of Limoges, France
- Prof. Deep M. Jariwala, University of Pennsylvania, USA
- Prof. Xinran Wang, Nanjing University, China
Responsible T-NANO Senior Editor: Prof. Sorin Cotofana