Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
The IEEE Transactions on Nanotechnology (TNANO) seeks original manuscripts for a Special Section following the 2018 edition of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).
The continuous scaling of CMOS devices as well as the increased interest in the use of emerging technologies make more and more important the topics related to defect and fault tolerance in VLSI and nanotechnology systems. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation, are of interest.
The topics of interest for this special issue include, but are not limited to:
- Yield Analysis and Modeling
- Testing Techniques
- Design For Testability in IC Design
- Error Detection, Correction, and Recovery
- Dependability Analysis and Validation
- Repair, Restructuring and Reconfiguration
- Defect and Fault Tolerance
- Totally Fail-Safe Design for Critical Applications
- Emerging Technologies
- Hardware Security
Authors who presented their work at DFTS are requested to significantly expand the previous conference version to contain substantial new technical material, as per TNANO and IEEE restrictions on duplicated publications and the competitive acceptance process. Manuscripts for the TNANO Special Issue/Section must be submitted on-line using the IEEE TNANO manuscript template and “Information for Authors”, via the IEEE Manuscript Central found at https://mc.manuscriptcentral.com/tnano. On submission to TNANO, authors should select the “Special Issue” manuscript type instead of “Regular Paper.”.
Please note the following important dates.
- Submission of papers:
20 December, 201820 January, 2019
- Notification of first review results: 20 March, 2019
- Submission of revised papers: 1 May, 2019
- Notification of final review results: 1 June, 2019.
Please address all other correspondence regarding this special Section to the Guest Editors.
Marco Ottavi (University of Rome Tor Vergata, IT) firstname.lastname@example.org
Vilas Sridharan (AMD, USA) email@example.com
Spyros Tragoudas (Southern Illinois University, USA) firstname.lastname@example.org