TNANO & TETC Joint Special Section
Joint Special Section on VLSI and Nanotechnology Design Trends for Computing Innovations
IEEE Transactions on Nanotechnology and IEEE Transactions on Emerging Topics in Computing seek original manuscripts for a Special Section tentatively scheduled to appear in the September 2017 issues. The topics of interest for this special section include:
- VLSI Design: Design of ASICs, microprocessors/micro-architectures, embedded processors, digital systems, NoC, interconnects, memories, and FPGAs.
- VLSI Circuits: digital circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits.
- Low Power and Power Aware Design: Circuits, micro-architectural techniques, thermal estimation and optimization, power estimation methodologies, and CAD tools.
- Computer-Aided Design (CAD): Hardware /software co-design, logic and behavioral synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floor planning, compaction), algorithms and complexity.
- Testing, Reliability, Fault-Tolerance: Digital testing, design for testability and reliability, online testing techniques, static and dynamic defect- and fault-recoverability, and variation-aware design.
- Emerging Technologies & Post-CMOS VLSI: Analysis, circuits and architectures, modeling, CAD tools and design methodologies for nanotechnologies, molecular electronics, quantum devices, biologically-inspired computing, spintronic technology, CNT, MTJ, NML, PCM, PMC, and sensor and sensor networks, etc.
Submitted articles must not have been previously published or currently submitted for journal publication elsewhere. An extended version of an article appearing in a conference proceedings (and in particular, GLSVLSI 2016) can be submitted provided that it has substantially new content w.r.t. to the original conference version. The conference paper must be cited in the main text and the cover letter must clearly describe the differences with the conference version and clearly identify the new contributions. As an author, you are responsible for understanding and adhering to the submission guidelines. Authors are invited to submit manuscripts focused on topics of computing directly to Transactions on Emerging Topics in Computing (TETC) at https://mc.manuscriptcentral.com/tetc-cs and papers focused on topics of nanoscale circuits and technology directly to Transactions on Nanotechnology (TNano) at https://mc.manuscriptcentral.com/tnano. Authors should be aware that papers can be published in TNano or TETC depending on the availability of space with the final allocation at the discretion of the Editor-in-Chief of the respective Transactions. Please address all correspondence regarding this Special Section to the Guest Editors (email: firstname.lastname@example.org).
The following is the tentative timeline for the special issue:
- Submission Deadline: September 30, 2016
- Author Notification: December 1, 2016
- Revised Manuscript Due: February 1, 2017
- Notification of Acceptance: May 1, 2017
- Final Manuscript Due: June 1, 2017
- Tentative Publication Date: September 2017
Laleh Behjat, University of Calgary,
Ayse Coskun, Boston University
Jie Han, University of Alberta
Martin Margala, University of Massachusetts Lowell
See Call for Papers here.